In a conventional microprocessor, the requirements of a plurality of interruptions generated from sections external and internal to the microprocessor are treated in accordance with a priority based on the importance and urgency thereof.
FIG. 1 shows the construction of a microprocessor for processing a plurality of interruptions. In FIG. 1, the plurality of interrupt requirements have their respective priorities which are supplied by an interrupt control circuit 1. The microprocessor 2 processes the interruptions in accordance with the interrupt priority signals generated by the interrupt control circuit 1 for receiving the plurality of interrupt requirements.
When the plurality of interrupt requirement signals are supplied to the interrupt control circuit 1, the interrupt control circuit 1 supplies to the microprocessor 2 an interrupt priority signals which indicate the priority of the interrupt requirement having a highest priority among the supplied interrupt requirements. When the microprocessor 2 receives the interrupt priority signals, the microprocessor judges whether this interrupt requirement has a priority to be processed, on the basis of the information of an interrupt priority control field (mask) in a control register disposed within the microprocessor 2. The mask holds a priority level which indicates the lowest limit of the interrupt priority to be processed, and is handled by a program. If the requirement does not have sufficient priority to be processed as a result of the judgment, the interrupt requirement is not processed until the mask information is changed to be less than the priority of the interrupt requirement by a program processed in the microprocessor 2.
When the mask information is changed to have the priority of the interrupt requirement, the interrupt requirement is processed. In this case, the next interrupt requirement is not processed until the former interrupt requirement has been processed, even if the priority of next interrupt requirement is higher than that of the former.
As mentioned above, in the conventional microprocessor, once the interrupt priority signals of the interrupt requirement are supplied to the microprocessor 2, the higher priority of next interrupt requirement is not processed until the former interrupt requirement has been processed.
Accordingly, even when the former interrupt requirement is waiting to be processed, and the interrupt control circuit 1 receives a next interrupt requirement having a priority higher than the priority of the former interrupt requirement, the interrupt control circuit 1 cannot change the interrupt priority signals to be those of the higher priority of the next interrupt requirement, so that the interrupt requirement having the higher priority cannot be processed until the waiting interrupt requirement has been processed.
Accordingly, in the conventional microprocessor, the interrupt requirement cannot be processed in accordance with priority at the real time.